The present invention relates to a semiconductor device as a single-chip implementation of dynamic random access memories (DRAMs) and logic circuits integrated together.
Thanks to recent tremendous increase in the number of, or the density per unit area of, components included within a single semiconductor integrated circuit, a so-called xe2x80x9csystem LSIxe2x80x9d, that is, an LSI with a multiplicity of functional blocks integrated together within a single chip, has become widespread in the art. Among other things, a hybrid LSI, or a single-chip implementation of large-scale logic circuits and DRAMs integrated together, has attracted great attention. A hybrid LSI including a plurality of built-in DRAMs, each performing an equivalent function expected from a conventional general-purpose DRAM, has already been put on the market.
If a number of DRAMs are integrated together on a single chip in this way, then external pins, which have been used as test terminals connected to a general-purpose DRAM, are no longer necessary. That is to say, the number of external terminals applicable to testing each of these DRAMs on a single chip is now limited. Thus, in testing these DRAMs, the number of terminals needed to test each of them should be reduced in some way or other. For example, according to a technique, these DRAMs are serially tested in a time-sharing manner. Alternatively or additionally, the DRAMs are tested while sharing as large a number of external test terminals as possible.
FIG. 13 illustrates an exemplary test scheme applicable to testing each one of DRAMs integrated on a single chip to make up a semiconductor integrated circuit.
Generally speaking, a DRAM usually performs automatic and self-refresh test functions. Thus, the test scheme illustrated in FIG. 13 is supposed to test a semiconductor integrated circuit with these two test functions.
In this specification, the xe2x80x9cauto refresh test functionxe2x80x9d means refreshing data stored in each memory cell within a DRAM by accessing the memory cell automatically. More specifically, the memory cell is accessed by periodically inputting a rectangular wave through a particular input terminal (i.e., an auto refresh input terminal) and getting a row address generated by an address counter within the DRAM (i.e., a refresh counter) responsive to the input wave.
The xe2x80x9cself-refresh test functionxe2x80x9d also means refreshing data stored in each memory cell within a DRAM by accessing the memory cell. More specifically, the memory cell is accessed responsive to a periodic wave (i.e., a row address sync signal) generated by an oscillator within the DRAM with the level of a self-refresh signal received at a particular input terminal (i.e., a self-refresh input terminal) fixed at the xe2x80x9cHxe2x80x9d or xe2x80x9cLxe2x80x9d level.
As shown in FIG. 13, a test scheme is provided to test a plurality of semiconductor memory deices 250A, 250B, . . . , 250X (i.e., DRAMs) included within a conventional semiconductor integrated circuit 200. Each of these semiconductor memory devices 250 includes a set of nine input terminals 201, 202, 203, 204, 205, 206, 207, 208 and 209. Specifically, an inverted row address strobe signal /RAS (i.e., a signal provided to test the operation of the DRAM) is received at the input terminal 201. An auto refresh test control signal PRAUT is received at the input terminal 202. A self-refresh test control signal SLF is received at the input terminal 203. An inverted column address strobe signal /CAS is received at the input terminal 204. An address ADR is received at the input terminal 205. An inverted write enable signal /WE is received at the input terminal 206. An inverted output enable signal /OE is received at the input terminal 207. A clock signal CLK is received at the input terminal 208. And a test control signal TEST is received at the input terminal 209. The test control signal TEST is provided to determine whether a burn-in test or an ordinary DRAM test should be performed.
On the other hand, the chip, or the semiconductor integrated circuit 200, includes a set of external terminals 211, 212, 213, 214, 215, 216, 217, 218 and 219 for inputting these signals therethrough. Specifically, the external terminals 211A, 211B, . . . , 211X are provided for inputting the inverted row address strobe signal /RAS to the individual semiconductor memory devices 250A through 250X, respectively. The external terminals 212A, 212B, . . . , 212X are provided for inputting the auto refresh test control signal PRAUT to the individual semiconductor memory devices 250A through 250X, respectively. The external terminal 213 is provided for inputting the self-refresh test control signal SLF in common to all the semiconductor memory devices 250A through 250X. The external terminal 214 is provided for inputting the inverted column address strobe signal /CAS in common to all the semiconductor memory devices 250A through 250X. The external terminal 215 is provided for inputting the address ADR in common to all the semiconductor memory devices 250A through 250X. The external terminal 216 is provided for inputting the inverted write enable signal /WE in common to all the semiconductor memory devices 250A through 250X. The external terminal 217 is provided for inputting the inverted output enable signal /OE in common to all the semiconductor memory devices 250A through 250X. The external terminal 218 is provided for inputting the clock signal CLK in common to all the semiconductor memory devices 250A through 250X. And the external terminal 219 is provided for inputting the test control signal TEST in common to all the semiconductor memory devices 250A through 250X.
That is to say, in this arrangement, the total number of external terminals is minimized by connecting the set of input terminals 203 through 209 in each of the semiconductor memory devices 250A through 250X to the respective common external terminals 213 through 219.
In addition, each of these semiconductor memory devices 250A through 250X includes a test data (TDQ) input/output terminal 221.
On the output end of the semiconductor integrated circuit 200, the test data input/output terminals 221 of all the semiconductor memory devices 250A through 250X are connected in common to a single set of external terminals 231 through an input/output bus 241.
On the input end of the semiconductor integrated circuit 200 provided with such a test scheme, when the inverted row address strobe signal /RAS is asserted (e.g., falls to the xe2x80x9cLxe2x80x9d level), an associated DRAM is activated. When the signal /RAS is negated (e.g., rises to the xe2x80x9cHxe2x80x9d level), the associated DRAM enters a standby mode. Accordingly, if the DRAMs are serially tested one by one in a time-sharing fashion, then the number of terminals needed for testing can be cut down by taking advantage of this function. That is to say, as shown in FIG. 13, the dedicated inverted row address strobe signal external terminals 211A through 211X are provided for the DRAMs 250A through 250X, respectively. And a test is carried out by asserting only the inverted row address strobe signal /RAS associated with the DRAM under test while negating the inverted row address strobe signals /RAS associated with the other DRAMs. In such a case, the external terminals 213 through 219 for inputting the signals other than the inverted row address strobe signal /RAS and the auto refresh test control signal PRAUT can be shared among all the semiconductor memory devices 250A through 250X.
Also, when the inverted row address strobe signal /RAS is negated, the associated DRAM comes to have a high impedance HIZ. Thus, on the output end of the semiconductor integrated circuit 200, only a DRAM associated with an asserted inverted row address strobe signal /RAS is accessed through the test data input/output bus 241. Accordingly, the external terminal 231 for the test data input/output bus 241 can also be used in common.
Thus, just one set of external terminals 231 connected to the test data input/output bus 241 is required on the output end of the semiconductor integrated circuit 200. For example, when the bit width of the bus 241 is 8 bits, only a set of eight external terminals 231 is needed.
As can be seen, according to the test scheme shown in FIG. 13, it is possible to considerably reduce the number of external terminals needed to test the semiconductor integrated circuit 200 including the semiconductor memory devices (DRAMs) 250A through 250X.
On its input end, however, the conventional semiconductor integrated circuit 200 requires the same number of external terminals 212A through 212X for auto refresh test control signals as that of the DRAMs integrated on the single chip. Accordingly, the number of terminals needed for a test cannot be minimized. Also, as the case may be, a required minimum number of terminals cannot be ensured in carrying out a test.
Nevertheless, if the auto refresh test control signal PRAUT is input through a common external terminal, then all the DRAMs are refreshed automatically at a time and therefore it takes a very long time to finish the test. In addition, while the auto refresh function of a DRAM is being tested, no other DRAM can be tested for other items.
Thus, in the arrangement shown in FIG. 13, the individual external terminals 212A through 212X are provided for the auto refresh test control signal PRAUT. In this manner, even while a DRAM is being tested for a certain item other than auto refresh, any other DRAM can be automatically refreshed in the prescribed access order.
Also, since the common test data input/output bus 241 is applied to all the DRAMs (i.e., semiconductor memory devices) 250A through 250X, the bus 241 is floating (at an intermediate potential level) during a normal operation of the integrated circuit 200, i.e., when the bus 241 is not used. Accordingly, if the bus 241 is connected to p- and n-channel MOSFETs of a CMOS inverter, for example, then these MOSFETs might be both turned ON and a feedthrough current might possibly flow.
An object of the present invention is cutting down the number of terminals required for testing and so on by getting all the DRAMs integrated on the same chip automatically refreshed independently even if a single auto refresh control signal terminal is shared among the DRAMs.
Another object of the present invention is sharing as many terminals as possible, which are connected to other terminals newly provided for a DRAM.
A first exemplary semiconductor device according to the present invention includes a plurality of DRAMs and logic circuits integrated together on a single semiconductor substrate. Each said DRAM includes a plurality of memory cells. The semiconductor device further includes a plurality of first terminals and a single second terminal. Each said first terminal independently provides a corresponding row address strobe signal to associated one of the DRAMs. The second terminal receives an auto refresh control signal for all the memory cells in the respective DRAMs. The semiconductor device further includes means for selectively generating an internal auto refresh control signal or an internal row address strobe signal from the corresponding row address strobe signal depending on whether the auto refresh control signal is asserted or negated. The generating means is provided for each said DRAM and connected to associated one of the first terminals and to the second terminal.
According to the first semiconductor device, an operation requiring a row address strobe signal (i.e., a signal applied to select a row address) and an auto refresh operation not requiring the row address can be performed in a time-sharing fashion. As a result, the test time can be shortened just like a conventional semiconductor memory device. In addition, since the second terminal receiving the auto refresh control signal is sharable among all the DRAMs, the number of terminals required can be cut down.
A second exemplary semiconductor device according to the present invention also includes a plurality of DRAMs and logic circuits integrated together on a single semiconductor substrate. Each said DRAM includes a plurality of memory cells and generates a self-refresh row address strobe signal to access a desired one of the memory cells responsive to a self-refresh control signal. The semiconductor device further includes: a data bus for inputting or outputting data to/from the DRAMs therethrough; and means for selectively outputting the self-refresh row address strobe signal to the data bus.
In the second semiconductor device, even if the self-refresh row address strobe signal should be generated independently for the respective DRAMs, there is no need to provide an additional output terminal for that purpose.
In one embodiment of the present invention, the data bus may be connected in common to the DRAMs, and the outputting means may output the self-refresh row address strobe signal associated with one of the DRAMs through a one-bit-equivalent signal line of the data bus.
A third exemplary semiconductor device according to the present invention includes a plurality of DRAMs and logic circuits integrated together on a single semiconductor substrate. Each said DRAM includes a plurality of memory cells and internally generates a pass/fail flag signal representing a test result. The semiconductor device further includes: a data bus for inputting or outputting data to/from the DRAMs therethrough; and means for selectively outputting the pass/fail flag signal to the data bus.
In one embodiment of the present invention, the pass/fail flag signal may represent a result of a burn-in test.
In another embodiment of the present invention, the data bus may be connected in common to the DRAMs, and the outputting means may output the pass/fail flag signal associated with one of the DRAMs through a one-bit-equivalent signal line of the data bus.